The disclosure relates generally to structures and manufacturing processes for field effect transistors (FETs). More specifically, embodiments of the present disclosure include a sloped finFET structure, and processes for fabricating the sloped finFET structure.
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current between the source and the drain can be turned on and off. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET structure is a “FinFET,” typically formed upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FinFET can include a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting as a drain terminal. A gate structure, which may be at least partially conductive, can be formed around one or more of the semiconductor fins. By applying a voltage to the gate structure, an electrically conductive channel can be created between the source and drain terminals of each fin in contact with the gate.
Over time, improvements to the structure and performance of a transistor, in addition to the ever-decreasing size of these components, have presented significant technical and manufacturing challenges. FinFETs in particular present conflicting demands for high yield processes and high-performance FETs. For example, designing the fin structures in a finFET as vertical elements can offer accurate and stable performance during operation. At the same time, these vertical elements can impede some manufacturing processes. For example, vertical sidewalls may impede the forming of source and drain contacts, spacer fabrication, epitaxial growth, and may also create additional electrical resistance during operation.